Silicon nitride layers have been conventionally available only with an amorphous structure. Recently, we successfully realized a monolayer silicon nitride with a crystalline structure.

The National Institute of Advanced Industrial Science and Technology (AIST), in a joint effort with the Joint Research Center for Atom Technology (JRCAT), developed a new process for direct thermal nitridation that employs gas mixture of nitrogen and hydrogen. The process realized , for the first time, the formation of monolayer silicon nitride with a crystalline structure on Si(001) substrate.

Silicon nitride layers, which play a key role in the ULSI (Ultra large scale integrated circuit) process, develop an amorphous structure when thinly formed on the surface of a silicon wafer, and uniformity drops as layer thickness decreases.

This new technique will be enable the complete control of the structure of a ultra thin silicon nitride layer and promise to help make ULSI devices more compact.

LSI (Large scale integrated circuit) devices are used in a great variety of products. Increases in the functionality and information requirements of PCs, game consoles, and other home computing devices have sparked a huge demand for high-performance LSI devices.

The scaling rule governing LSI design have been key in boosting LSI performance-a uniform down scaling of the transistors in an LSI device translates into an increase in performance. The time electrons require to traverse a transistor falls as that transistor becomes smaller, and processor speed grows as a consequence, but the scaling rule allows for no increase in performance from a mere shrinking of the path of electron flow. Instead, a transistor must be shrunk in all three dimensions to bring results. For instance, if the channel length is halved, so must be the channel width and the gate oxide layer. Knowing that further down scaling is the way to elevate LSI device speed and performance, semiconductor manufacturers have boosted LSI device performance in accordance with the scaling rule.

But these steady improvements in performance have reached the edge of the envelope. The minimum width of the electric wiring covering the silicon surface of mainstream LSI devices stands around 0.13 micro-m, while the thickness of the silicon dioxide which is used as the gate insulating layer comprising such LSI devices ranges from 1.5 to 2 nm. The unit micro-m refers to the very short length of one-thousandth of a centimeter, while one nm is one thousand times shorter than a micrometer. The current wisdom calls for a gate insulating layer 0.6- to 0.8-nm thick in 2010 in order for LSI performance to grow in accordance with scaling principles. Such a thickness corresponds to a very thin silicon dioxide layer only three to four molecules thick.

At such thickness, these layers can no longer be expected to function as insulating layers because current flows right through them; this process is called the electron tunneling effect. Experts considering ways around this problem decided that a high-k material, which has a greater dielectric constant than silicon dioxide, should be used as the gate insulating layer. A high-k insulating layer can be of a greater thickness than an ultra-thin silicon dioxide layer-which is subject to the problem of electron tunneling-while not detracting from the benefits of down scaling. It was hoped that such a layer could reduce the direct tunneling current that plagues ultra-thin silicon oxide layers.

The greatest problem facing the use of a high-k material as a gate insulating layer is the reaction that occurs at the interface between the gate insulating layer and the silicon. The substances that show the most promising candidates of high-k materials are metal oxides, which when layered on a silicon wafer and heat treated react with the silicon at the interface to produce silicon dioxide and silicates of the metals. As such, no crisp interface was possible, and a high-k layer with a thickness corresponding to a 1-nm silicon dioxide layer could not be formed. These problems encouraged research on the mechanism behind interface reactions and surface treatments able to suppress such reactions.

Many attempts have been made to prevent this interface reaction by applying a variety of materials at the interface between the high-k and silicon. Recently, an ultra-thin silicon nitride layer inserted in the interface suppressed the reaction and consequently became the focus of attention. The layer's success is attributed to the strong bonding of the silicon nitride and the short distance between bonds, which suppresses the passage of oxygen and other elements.

Silicon nitride has a lower dielectric constant than high-k materials, so a thick nitride layer inserted at the interface plays a large part in determining the dielectric constant of the system, acting to keep the dielectric constant of the insulating layer as a whole low. This is why such layers must be made as thin as possible.

However, when an amorphous silicon nitride layer is formed on the Si(001) surface, which is conventionally used in CMOS products, and made as thin as possible, non-uniformity appear in the layer that allow some reaction at the interface. If silicon nitride is to be used as the interface layer, it must be not only as thin as possible but also uniform. Amorphous silicon nitride, however, is difficult to precisely apply.

AIST and JRCAT therefore teamed up to seek ways to produce an ultra-thin silicon nitride layer. Their efforts led to the development of a new direct thermal nitridation process that uses gas mixture of nitrogen and hydrogen. This process was used to form on the surface of silicon (001) the world's first one-molecule-thick silicon nitride layer with a crystalline structure (having a 2 x 2 periodic structure).