Photovoltaic Power Team

High-Performance PV Modules Based on Thin Crystalline Silicon Solar Cells

Over View

A large number of photovoltaic (PV) systems have been installed under the Feed-In Tariff (FIT) since July 2012.
In addition to the conventional installation on house rooftops, many large-scale or “mega solar” power plants have been constructed. It is very important to reduce the cost of PV power generation in order to reduce the share of the burden on electricity users and to improve the competitiveness of PV modules in the market.

Research Target

The team addresses the following subjects to develop technologies for producing low-cost, highly efficient and reliable modules (target conversion efficiency: 22%)

  • Silicon ingot slicing technology with high accuracy and reproducibility (thin wafer)
  • High-efficiency cell fabrication technique using thin Si wafers (PERC cell, back contact cell, etc.)
  • Technologies for improving the efficiency and reliability of PV modules (development of new materials, structures, etc.)

The team is also conducting research on “smart stack technology” to develop next-generation highly efficient solar cells (conversion efficiency higher than 30%). Technologies to achieve the power generation cost target of 14 yen/kWh in 2020 and 7 yen/kWh by 2030 will be developed.

Silicon ingot (left) and appearance after slicing (right)

Japan’s PV roadmap for 2030 (NEDO PV challenges)

Research Outline

Although crystalline silicon (c-Si) technology has the dominant share in the PV market, its cost must be reduced significantly in order to accelerate the deployment of PV systems.
The team conducts comprehensive research using a semi-production line from ingot slicing to module fabrication and testing.

  • Thin wafer fabrication technology

    The team is developing a slicing technology for thinner wafers with a thickness of about 0.10 mm (from the present cell thickness of 0.18 mm to 0.08‒0.10 mm).
    The team is also investigating the relationship between cracks and wafer strength to develop thin and tough wafers and to improve the yield during cell processes such as wafer cleaning.

    Silicon ingot (left) and appearance after slicing (right)
    Silicon ingot (left) and appearance after slicing (right)
    (wafer thickness: 0.12mm)

  • Development of new cell fabrication techniques

    New cell production processes using the ion implantation technique have been developed in addition to the conventional thermal diffusion process. The effective use of ion implantation can reduce the number of cell processes during back-contact cell fabrication.

  • Improvement in module reliability and development of a new evaluation method

    A new nondestructive module evaluation method through voltage mapping using the absolute electroluminescence (EL) method has been developed. A forward bias is applied to the solar cell and individual cell voltages can be evaluated based on the luminescence intensity of the cells.

    Voltage mapping using the absolute electroluminescence method
    Voltage mapping using the absolute electroluminescence method

  • Next-generation multi-junction solar cell“smart stack technology”

    The “smart stack technology” using metal nanoparticle arrays has been developed, making the interconnection of various solar cells with different materials and bandgaps possible for the first time. This provides flexibility in material choice and device design because the mismatch in lattice constants, thermal expansion coefficients, etc. can be disregarded with this technique.

    Smart stack technology

    Smart stack technology

    A GaAs/InP-based four-junction solar cell has achieved conversion efficiency as high as 31.6%, and a GaAs/CIGS-based three-junction solar cell has achieved conversion efficiency as high as 24.2% (joint research with the Research Center for Photovoltaics at AIST Tsukuba Center). We are working to improve and establish this technology for mass production.
    The use of thin crystalline silicon as a bottom cell provides high efficiency and low-cost multi-junction cells. The team is developing crystalline silicon based smart stack cells that go beyond the theoretical efficiency limit of single-junction crystalline silicon solar cells (29%). A demonstration GaAs/Si three-junction cell with conversion efficiency of 24.7% has been successfully fabricated.

    GaAs/Si-based three-junction smart stack cell

    GaAs/Si-based three-junction smart stack cell

Main Research Facilities

Electrode firing furnace Spin etching apparatus Ion implantation equipment
Electrode firing furnace Spin etching apparatus Ion implantation equipment
Furnace for forming contacts between the electrode and the diffusion layer as well as Al‒BSF layers. Apparatus that etches a single side of the wafer by spin rotation. Only one side can be etched without a protective film. Equipment that implants accelerated phosphorus or boron ions in the wafer. The diffusion profile can be precisely controlled.

Major Achievements

  • 1) The standard FREA process for the fabrication of Al‒BSF type crystalline Si cells was established with an average efficiency of about 19.3%, equivalent to the highest efficiencies reported by companies.
  • 2) The technology for thin wafer (0.12 mm thick) slicing from silicon ingots has been established using diamond wires. Processing conditions close to the mass production of a wafer with a thickness of 0.12 mm have been established with a 99.8% yield.
  • 3) The smart stack technology was applied to a GaAs/Si-based three-junction cell to achieve conversion efficiency as high as 24.7%.
  • 4) Industrializable fabrication processes for PERC-type cells and bifacial-type cells were established with efficiencies of 20.5% and 20%, respectively.
  • 5) A diffusion layer with a uniform depth on pyramid-shaped surfaces has been successfully formed by means of ion implantation, demonstrating cell efficiency as high as 19.4%.
  • 6) New cell and module evaluation techniques (absolute EL method and internal quantum efficiency mapping method) were developed. The absolute EL method can be used to visualize energy losses in smart stack cells.
Crystalline silicon cell fabricated by standard FREA process
Crystalline silicon cell fabricated by standard FREA process
Phosphorus diffusion layer formed by ion implantation
Phosphorus diffusion layer formed by ion implantation

Team Member

Title Name
Leader Hidetaka Takato
Senior Researcher Hidenori Mizuno
Researcher Toshimitsu Mochizuki
Researcher Tomihisa Tachibana
Researcher Joonwichien Supawan
Researcher Kenji Kamide