National Institute of Advanced Industrial Science and Technology (AIST)

産総研トップへ

Photovoltaic Power Team

High-Performance PV Modules Based on Thin Crystalline Silicon Solar Cells

Over View

 A large number of photovoltaic (PV) systems have been installed under Feed-In Tariff (FIT) since July 2012. In addition to the conventional installation on house rooftops, many large-scale power plants so called “mega solar” have been constructed. Reduction in PV power generation cost is very important to reduce the burden share of electricity users and to improve the competitiveness of PV modules in the market.

Research Target

 The team addresses the following subjects to develop technologies for producing low-cost, highly efficient and reliable modules (target conversion efficiency: 22%)
  • Silicon ingot slicing technology with high accuracy and reproducibility (thin wafer)
  • High efficiency cell fabrication technique using thin Si wafers (PERC cell, Back contact cell etc.)
  • Technologies for improving the efficiency and reliability of PV modules (development of new materials, structures, etc.)
 The team is also focusing on the research of “smart stack technology” to develop a next-generation highly efficient solar cells (conversion efficiency higher than 30%). The technologies to achieve the power generation cost target of 14 JPY/kWh in 2020 and 7 JPY/kWh by 2030 will be developed.
Japanese PV roadmap for 2030 (NEDO PV challenges)

Japanese PV roadmap for 2030 (NEDO PV challenges)

Research Outline

 Though the crystalline silicon (c-Si) technology dominates the share in the PV-market, it requires significant cost reduction in order to accelerate the deployment of PV systems.
 The team conducts comprehensive research using a semi-production line from ingot slicing to module fabrication and testing.
  • Thin wafer fabrication technology

     The team is developing a slicing technology for thinner wafers with thicknesses of about 0.10 mm (from the present cell thickness of 0.18 mm to 0.08-0.10 mm).
     The team also investigates the relationship between the cracks and the wafer strength to develop thin and tough wafers and to improve the yield during the cell processes such as the wafer cleaning.

  • Development of new cell fabrication techniques

     New cell production processes using the ion implantation technique have been developed in addition to the conventional thermal diffusion process. The effective use of the ion implantation can make possible the reduction of the number of cell processes during the back-contact cell fabrication.

  • Improvement in module reliability and development of a new evaluation method

     A new nondestructive module evaluation method through the voltage mapping using the absolute electroluminescence (EL) method has been developed. A forward bias is applied to the solar cell and individual cell voltages can be evaluated from the luminescence intensity of the cells, and this technique is nondestructive.

  • Next-generation multijunction solar cell “smart stack technology”

     The “smart stack technology” using metal nanoparticle arrays has been developed, for the first time, making possible the interconnection of various solar cells based on different materials and bandgaps. It can provide the flexibility in material choice and device design because the mismatch in lattice constants, thermal expansion coefficients, etc., can be neglected in this technique.
     A GaAs/InP-based four-junction solar cell has achieved a conversion efficiency of as high as 31.6%, and a GaAs/CIGS-based three-junction solar cell has achieved a conversion efficiency of as high as 24.2% (joint research with the Research Center for Photovoltaics at AIST Tsukuba Center). We are aiming to improve and establish this technology for mass production.
     The use of thin crystalline silicon as a bottom cell provides high efficiency and low cost multijunction cells. The team is developing the crystalline silicon based smart stack cells that goes beyond the theoretical limit efficiency of single junction crystalline silicon solar cells. The demonstrative GaAs/Si three-junction with a conversion efficiency of 24.7% was successfully fabricated.

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Figure of thinning process of wafer (cell)

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Voltage mapping by the absolute electroluminescence method
Figure of thinning process of wafer (cell) Voltage mapping by the absolute electroluminescence method

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Smart stack technology

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GaAs/Si-based two junction smart stack cell
Smart stack technology GaAs/Si-based three-junction smart stack cell

Main Research Facilities

Electrode firing furnace Spin etching apparatus Ion implantation equipment
Electrode firing furnace Spin etching apparatus Ion implantation equipment
A furnace for forming contacts between the electrode and the diffusion layer as well as Al-BSF layers An apparatus that etches a single side of the wafer by spin rotation. Only one side can be etched without a protective film An equipment which implants accelerated phosphorus or boron ions into the wafer. The diffusion profile can be precisely controlled

Activities and Achievements

  • The facilities for crystalline Si solar cell and module fabrication have been installed and started operation. The FREA standard cells with Al-BSF have been fabricated with an average cell efficiency of about 19.3% equivalent to the best reported efficiencies from mass-production
  • The thin wafer (0.12 mm thick) slicing technique from silicon ingots has been established using diamond wires. The processing conditions close to the mass production of the wafer with the thickness of 0.12 mm have been established with a 99.8% yield.
  • The smart stack technology was applied to a GaAs/Si-based three-junction cell to achieve a conversion efficiency of as high as 24.7%.
  • 0.1 mm-thick double-sided solar cells have been fabricated.
  • A diffusion layer with a uniform depth on pyramid-shape surfaces has been formed successfully by means of ion implantation, demonstrating cell efficiencies of as high as 19.1%.
  • A new module evaluation technique was developed (absolute EL method, an in-situ AC impedance measurement method). The place of failure can be identified nondestructively, and the voltage of each cell within a module can be evaluated individually.
Outlook of a crystalline silicon cell by standard FREA process Phosphorus diffusion layer formed by the ion implantation
Outlook of a crystalline silicon cell by standard FREA process Phosphorus diffusion layer formed by the ion implantation

Team Member

Title Name
Leader Hidetaka Takato
Senior Researcher Katsuto Tanahashi
Researcher Hidenori Mizuno
Researcher Mitchell Jonathon
Researcher Toshimitsu Mochizuki
Researcher Tomihisa Tachibana
Researcher Joonwichien Supawan