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Vol.3 No.3 2010

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Research paper : A methodology for improving reliability of complex systems (A. Katoh et al.)−209−Synthesiology - English edition Vol.3 No.3 (2010) Term 12.Term 13.Term 14.Term 15.Term 16.Term 17.Term 18.Term 19.Term 20.Term 21.Term 22.Term 23.Term 24.Term 25.Term 26.Structured analysis and structured design (SA/SD) method: a design method where a system is decomposed into components by focusing on data flows of the system.ISO 15288: one of the systems engineering standards. The tasks and procedures are defined for each process of the entire system lifecycle from the conceptualizing phase to the dismantling phase.ANSI/EIA 632: one of the systems engineering standards. The tasks and procedures are defined for each process of the system lifecycle from the conceptualizing phase to the transition to operation phase.IEEE 1220: one of the systems engineering standards. The tasks and procedures are defined for each process of the system lifecycle from the system requirement analysis phase to the system test phase.Test method: a verification method for verifying behavior of actual products against the test cases.Simulation method: a verification method where a target to be verified and peripheral environment of the target are simulated as models on a computer, and behavior of the models is verified against the test cases.Deadlock: a state where two or more processing units wait for each other to complete each processing, and as a result, all processings fail to move on further.Functional designing: a work where functions defined as a system specification are decomposed and refined, and performances defined as the system specification are allocated to the decomposed and refined functions.Physical designing: a work where system components are specified, and the functions and performances decomposed and refined in functional designing are allocated to the components.Functional analysis: the process which corresponds to functional designing, defined in chapter 6 section 3 in IEEE1220.Synthesis: the process which corresponds to physical designing, defined in chapter 6 section 5 in IEEE1220.Bridge method: a method which is presented in this paper to connect architectural design method and model checking seamlessly.Traceability matrix: a table which summarizes the correspondence of upper and lower level specifications.Finite automaton: a behavior model composed of finite number of combinations of the state, transition, and operation.Timed automaton: a behavior model where temporal variables are incorporated into finite automaton. It allows modeling of the time passage as transition conditions.SPIN: a model checking tool based on finite automaton. State transitions of the system are modeled using PROMELA (process meta language) which is a language similar to C. It can be downloaded from .UPPAAL: a model checking tool based on timed automaton. State transitions of the system can be modeled in an intuitive manner using GUI (graphical user interface). It can be downloaded from .Industrial robot: an industrial-use machine with the auto-control functions for manipulation or transportation. It can be programmed to conduct various work routines.Subsystem: an entity possessing the structure of a distinct, local system, while being part of a system.Subsystem Component: an element or a part which composes the subsystem.COTS (commercial off the shelf): software and hardware products which are available on the market.Teaching pendant: a device used for programming acitons and emergency stop of an industrial robot.Console: an input and output device used for operating the system. It is composed of input device such as a keyboard and output device such as a monitor display.QCD: an abbreviation for quality, cost, and delivery of development.Temporal logic: a theory of rules and expressions to understand and express the problem in relation to time. Temporal operator, path quantifier, and logic operator are combined to express the properties such as “P is always valid” or “Q is eventually valid.”Temporal operator: operators to express “G: globally” and “F: finally” in temporal logic.Path quantifier: operators to express “A: all” or “E: exists” in temporal logic.Logic operator: symbols which express logic operation. It includes “NOT: negation”, “AND: logical product” and “OR: logical sum.”Term 27.Term 28.Term 29.Term 30.Term 31.Term 32.Term 33.Term 34.Term 35.Term 36.Term 37.Term 38.Term 39.International council on systems engineering (INCOSE): INCOSE Systems Engineering Handbook version 3.1, 1.5 of 6, INCOSE, USA (2007).N. G. Leveson: SAFEWARE: System Safety and Computers, 515-553, Addison-Wesley Professional, USA (1995).H. Shimizu: Arian 5 no bakuhatsu jiko to sofuto uea anzensei ni kansuru kokusai kikaku (Explosion of Ariane 5 and the international standard for software safety), Anzen Kogaku (Journal of the Japan Society for Safety Engineering), 41 (1), 39-42 (2002) (in Japanese).Ministry of Land, Infrastructure, Transport and Tourism: FDP shisutemu no shogai no gen’in chosei no kekka (Result [1][2][3][4]References

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