Vol.3 No.4 2011

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Research paper : R&D of SiC semiconductor power devices and strategy towards their practical utilization (K. Arai)−250−Synthesiology - English edition Vol.3 No.4 (2011) Ultralow Loss Power Device Technology: Practical use survey of the future power semiconductor device”, FY1998~2002, ENAA). This activity promoted the exchange between the basic research and application fields, and we were able to make prospects that SiC was superior in principle against silicon in the industrial application of the power devices.To widely spread these results, these results were comprehensively described in a book[4].3.2 Strategies and results of AIST period (2001~2007)- Proposal of a total solution from wafers to a system -There were two years left of the NEDO project, and a structural organization from the Agency of Industrial Science and Technology to the National Institute of Advanced Industrial Science and Technology occurred in 2001. In this reorganization, the research centers were designed as units with specific missions. In this R&D phase, we were beginning to see the prospects of the SiC power device. Whether the new device would be practically utilized in power electronics depended not only on the performance of the device, but it was clear that we needed to optimally integrate the various elemental technologies that tended to be at trade-off with each other (Fig. 7). During this period, R&D of power electronics in Japanese industry was difficult due to the reduced investment in infrastructure. For R&D for the practical utilization of the new power semiconductor device, the role of the public institution was important in the long-term R&D. With this thinking, we conducted an integrated basic R&D (total solution) in one research unit that included everything from material and device process development to converter and system application. We declared the realization of “the innovation of power electronics through innovative power device”, and established PERC composed of five groups.During the first half period of PERC, the effort was spent on achieving the goal of the “Ultralow Loss Power Device” project. This was incorporated into the goal of “the innovation of power electronics through innovative power device”, and the activities commenced fully. There were 14 full-time staff members, while there was no full-time staff in the Circuit and Implementation Team, and the researchers from other research units in AIST concurrently worked for the Implementation and System Application Teams. At the commencement, from the perspective of selection and concentration, there were questions raised about such an integrated approach. However, it was gradually accepted since one of the central tenets was the promotion of “Full Research based on Type 2 Basic Research” as declared by AIST. The staff was increased to 18 people in 2007, and combined with the full-time members and the five dual-duty researchers, there were over 80 people involved.When the “Ultralow Loss Power Device” project was completed, the R&D at AIST was continued as two topics of the NEDO open proposal for Energy Saving (FY 2003~2005), “Basic Research for Ultralow Loss Device, MOS Reliability and High Power Densification of Converter” and “Development of Advanced Diode”, jointly proposed with the corporations for further practical utilization. As a result, it continued on to the NEDO project “Basic Technology for the Power Electronics Inverter (or the “Inverter” project)” (FY 2005~2007). There, the demonstration of the converter was conducted with Mitsubishi Electric Corporation. R&Ds for the current capacity increase, high reliability (MOS oxidation film) to warrant the realization of the power device, and R&D to seek potential of high power densification of the converter were conducted with the corporations through the concentrated research method.Fig. 7 Various issues of the power module technologyThe various elemental issues are complexly interrelated, and must be solved concurrently (created by Ichiro Omura, Toshiba Corporation, Next-Generation Power Semiconductor Device Commission).Fig. 8 Fabrication technology of SiC monocrystal waferIncreasing the quality and decreasing the cost of wafer are the primary issues in the practical utilization of the SiC power device. For decreasing the cost, the development of peripheral technologies such as monocrystal cutting and polishing is also important.FrequencyCapacityBarrier of circuit implementationBarrier of wiringLossBarrier of EMI and electric stressBarrier of circuit topologyBarrier of semiconductor materialBarrier of device structureBarrier of reliabilityBarrier of electric resistance (parasitic factor)Barrier of thermal resistanceBarrier of temperatureBarrier of insulationAIST/PERC wafer Dislocation density: about 2000-500/cm2 Screw dislocation with micropipe: very smallCommercial wafer Dislocation density: about 10,000/cm2Atom force microscope image of the polished surface• High-speed and environment- friendly industrial polishing process• Flatness of the atomic orderSi face(0001) 4H-SiC ~0° offSi face(0001) 4H-SiC 8° offGrinding and polishingMonocrystalgrowth90 min~1 process90 min1 process~15 min1 process(CMP)Chemical mechanicalpolishing(wrapping)MechanicalpolishingGrindingCutting and shaping75 mm diameter monocrystal3-inch high-quality 4H-SiC waferLarge 4H-SiC monocrystal

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