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Research paper : R&D of SiC semiconductor power devices and strategy towards their practical utilization (K. Arai)−254−Synthesiology - English edition Vol.3 No.4 (2011) and telephone company (current Nippon Telegraph and Telephone Corporation), and the private companies joined to participate in research under their abundant research fund. Under such privileged technological development, the obtained technological result may be rather over-spec but still could be used to satisfy the demands in Japan. However, as the management tightened up due to increased free competition, the development intent of the companies dropped due to the limited domestic demand projection and reduction in R&D funds. The contraction and corporate merging of the infrastructure R&D occurred, and the R&D environment deteriorated rapidly for power electronics as a whole as well as for infrastructure R&D. Around the world, global corporations such as Siemens, ABB, GE, and others were spending efforts assuming the developing countries as their clients. With such industrial background, we believed the public research institution must play a critical role. Since AIST started from material research, the development of wafer and device process was conducted relatively smoothly. However, there were hardly any people who had experience developing the actual device that could be implemented to the converter, and this was only possible by inviting veteran researchers from industry. The presence of such invited researchers was extremely important in executing the total solution, along with the cooperation from the Energy Technology Research Institute, Nanoelectronics Research Institute, and Metrology Institute of Japan within AIST. The demonstration of the basic R&D as a whole in the “High-Tech Manufacturing” Research Program was a symbolic accomplishment of the total solution. The state-of-art joint research with the other research units of AIST through the AIST grant from the Ministry of Economy Trade and Industry (METI) played a major role in the construction of the facilities and the operation (“Development of Ultralow Loss Power Module Technology” (FY 2002~2006), “Development of On-CPU High-Speed High-Capacity Power Technology” (2004~2006), and “Development of Operation and Control Technology for Power Equalization System” (2003~2006)). The pioneering research that was conducted under the “IP Integration” research program, where the obtained patents were integrated, became a power in conducting further R&D for ultrahigh blocking voltage devices.The prospect for a central research center for Japan for power electronics, a major basic technology for future energy saving centering on the SiC power device development, at AIST was not available until 2008. One of the greatest reasons was the R&D prototype manufacturing line for fabricating and providing the prototype devices to places where application could be expected was not up to a satisfactory level. To realize this, the construction of a device foundry, as well as the participation and collaboration of the researchers in system application who can present the required specification for device performance is mandatory. Since 2008, the potential for the former is beginning to take shape as the Industrial Transformation Research Initiative. We hope for the realization of the latter.4.2.2 Improvement of device technology in the Open Proposal for Energy SavingAfter the first five years of the fundamental development project, the section in charge of the project at METI demanded faster practical utilization, and did not approve the continuation of the basic research by the project. At that time, the SiC power device was taken up as future technology in the “Strategy for Energy Saving Technology”Note 4. We also held a symposium where the government discussed the expectation for energy saving by the SiC power device and the user companies discussed the applications, to raise the interest for the practical utilization of SiCNote 5. This effort led to five topics of the three-year NEDO open proposal for Energy Saving with the collaboration between the industry and the government. In these three years, the companies were able to demonstrate several ampere (A) class devices, and AIST was able to do a principle demonstration of MOSFET as ultralow loss device. Also, high-performance Schottky barrier diode that can directly lead to the performance demonstration for the converter and PIN diode was developed. These results continued on to the development of the NEDO “Inverter” project.4.2.3 Establishment of ESICAT Japan, LLPWhile it is essential to form the high-quality epitaxial film with controlled impurities concentration for device fabrication, the supply of epitaxial wafer was dominated by Cree, Inc. In FY 2005, with the agreement for joint research support, Showa Denko K.K., a company with experience in epitaxial growth, the Central Research Institute of Electric Power Industry, and AIST got together and a limited liability partnership ESICAT Japan was established. The technological topic was the practical utilization of carbon-face micro off-angle-face epitaxial wafer developed by AIST. The aforementioned “Inverter” project did not include the wafer development, and the development support was done through the information exchange on the correlation between the device performance and the wafer quality, as well as supply from the Japanese wafer manufacturers. Fulfilling the expectation, the supply of high-quality four-inch substrate was started in Japan. In the final stages of the project, by fabricating the four-inch prototype of the Schottky barrier diode, it was demonstrated that the quality of the epitaxial wafer was at a practical level. These activities contributed to creating the supply chain for the epitaxial wafers in Japan.4.2.4 Coexistence with the GaN R&DIn the activities after 2001, we were occasionally forced to select between SiC and GaN. We stated that it was significant to visualize the innovations in power electronics while constantly comparing the advantages and disadvantages of

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