Vol.3 No.4 2011

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Research paper : R&D of SiC semiconductor power devices and strategy towards their practical utilization (K. Arai)−252−Synthesiology - English edition Vol.3 No.4 (2011) By the end of the project, the conditions for realizing the high power density converter of 50 W/cm3 were clarified. To set the milestone of the technological development at the research center, we utilized the “High-Tech Manufacturing” Research Program established by AIST to promote the manufacturing technology in 2006. There, the crystal substrate, epitaxial film, IEMOS and Schottky barrier diode device, and chopper circuit were fabricated jointly with the three research teams, to achieve the control of the generator motor and to verify the total solution (Fig. 12). For the JFET (SIT) and PIN diodes, there were no concern about the reliability of the gate oxide, and the fabrication technology was developed and obtained a yield that allowed the device to be supplied for the converter. The joint research for system application was started with the corporation around 2007, and the results have been obtained starting in 2008.3.2.3 Increased current capacity and reliability of the device and the wafer qualityFor the demonstration of the power device for its practical utilization, device chips of over 10 A to 100 A were required. At the point of 2005, reports of increased current capacity were starting to be heard for the Schottky barrier diode, while the development was delayed in the switching device. The quality of the wafer (such as crystal defect) was considered to be the major cause. Considering the result of the leading research for energy saving, the “Inverter” project set the goal of clarifying the wafer quality to achieve the high-capacity chip of 100 A class. In reality, the monocrystal substrate had about 10,000 /cm2 of crystal defects (dislocations). Therefore we worked to clarify the relationship with the crystal defects and the reliability of MOS and increased device capacity that was not studied seriously until then. The crystal defect evaluation using the synchrotron radiation light was deployed at AIST. We obtained the conclusion that while certain degree of reduction in crystal defects was desirable, we could go ahead with the current crystal quality through the advancement of growth technology of the epitaxial film formed on the crystal substrate for fabricating the device (minimization of the surface defect during epitaxial growth, conversion of the crystal defect type, etc.), and work on the device process (gate oxidation layer formation where both channel mobility and reliability are obtained, high-temperature ion implantation and post activation process, etc.).3.2.4 Construction of the converter design method and application to high power densificationThe conditions and environments in which the power electronics devices are used are varied, and optimizations were obtained by trial-and-error in the past developments. The desired performances of the devices differ according to the use. Particularly, the SiC power device is used for high-speed switching under the condition of high current and high blocking voltage, and the integrated design of device circuit, passive components, and converter structure to maximize the device performance is also important (Fig. 13). For example, at higher frequency, the effects of floating capacitance and floating reactance that did not have to be considered before manifest, and their evaluation and reduction become necessary. AIST developed the circuit integration design composed of device simulation, filter performance, control method, and others, and developed the “simulator for converter loss integrated design” in the “Inverter” project. Combined with the prototype evaluation of the low-loss SiC-MOSFET, we clarified the condition for the high power density of 50 W/cm3.3.3 Strategies and results of AIST period (2008~)- Resolving the bottleneck to the practical utilization -After 2008 at AIST, the wafer, device, and converter that completed the principle demonstration advanced to the downstream demonstration research, and this flow is an important approach for the practical utilization of SiC. During this period, AIST set as its goal the basic research with higher goal needed for the R&D that spiraled upward, DemonstrationChopper circuitMotor driven powergeneration experimentSublimationmethodIngotSiC powderEpitaxial growthEpitaxial waferCutting andpolishingBulk waferDicingBondingImplementationFabrication ofdevice circuitIon implantationDry etchingMetal vapor depositionHigh-speed thermal annealingDevice chip(MOSFET, SBD, etc.)IEMOS 10AGate circuitGate circuitSiC-MOSSiC-MOSSiC-SBDSiC-SBD200 µmSourceSourceGateGate 100 µm100 µm2-inch1 µm0001 nm1 nm0.5 nm0.5 nmFig. 12 Demonstration of the total solution by all PERC technology (wafer – device – converter) in the “High-Tech Manufacturing” Project (see text)IntegrateddesigndatabaseDesigninformationElectromagneticanalysisStructuralanalysisThermalanalysisOptimizationofintegrated lossDevicemaincircuitControlcircuitFiltercircuitCircuit integrateddesign platformSystem integrateddesign platformPassivecomponentsReliability ofhigh-temperatureoperation3DimplementationImplemented core technology design platformHigh-temperatureelectrode formationIntegrateddesignFig. 13 Conceptual diagram of the integrated design for power converterThe integrated loss of device – filter (magnet) – control is simulated. This will enable optimization of the loss in the circuit design. The integrated loss design simulation of the converter becomes possible by integrating the database of the passive components and the structural factors.

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