Vol.3 No.4 2011

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Research paper : R&D of SiC semiconductor power devices and strategy towards their practical utilization (K. Arai)−251−Synthesiology - English edition Vol.3 No.4 (2011) 3.2.1 Contribution to the wafer issueThe technologies developed in the project were published at the academic societies, and were actively transferred to industry. Considering the repeated A-face growth (RAF) method developed in Japan, developments were conducted to reduce the crystal defects and to increase the diameter. Also, the cutting and polishing technologies essential for the fabrication of the wafer and the technological transfer were conducted (Fig. 8). In epitaxy, it was found that the growth was possible in the off-less face on the C-face, and the mobility at the MOS interface formed on the C-face was high. To promote the practical use of the epitaxial technology based on these findings, a joint research system was formed by the Central Research Institute of Electric Power Industry, Showa Denko K.K., and AIST. A limited liability partnership (LLP) called the ESICAT Japan, was established based on this research to construct the epitaxial wafer supply system that was the rate-controlling factor of the R&D (that is the controlling factor of the turn around time of device fabrication), and to utilize these wafers in the “Inverter” project. This activity was turned over to Showa Denko in 2007.3.2.2 From principle demonstration of the power device to converterFor the switching device, the development of the junction FET (JFET) was conducted. Although the ampere class device was available on the market, it has not been widely used since it was a normally-on device (a device that is switched on at zero gate voltage). MOSFET has not been marketed since the MOS channel mobility can not be increased and the reliability of the oxidation layer is unclear. AIST developed the Implantation and Epitaxial MOSFET (IEMOS) by utilizing the epitaxial process of MOS channel by employing the high channel mobility of the carbon side, and succeeded in the principle demonstration of a device with world lowest loss. For JFET, using the imbedded gate structure (static induction transistor (SIT)) made by the epitaxial technology, we succeeded in the principle demonstration of low on-resistance to the level where further reduction of the substrate resistance would require further performance improvement (Figs. 9, 10 and 11). The device process technologies became intellectual properties, and were technologically transferred to industry as needed.For IEMOS, the prototype of the ampere class ultralow loss device was fabricated and supplied in the “Inverter” project. n+ n- n+ p+ n- n- p- Implanted low concentrationn-type layerImplanted high concentrationp-type layerGate oxidized filmformationLow concentration p-type epitaxial layer,4H-SiC(0001) faceEmbedded channelstructureDrainSource contactGate electrodeS. Harada et al; IEDM 2006, SF USA (2006-12) S. Harada et al; ISPSD 2007 ,Korea (2007-6)µm8642300.00 nmCrystallization of channel region is good, low concentration → High channel mobilityPyrogenic re-oxidation→ High channel mobilityPunch through control→ high blocking voltage→ High channel mobility→ Pinch off at low voltage, high pn junction withstand voltage→ high blocking voltagechannel layerVB=700 V @VG=-12 VVg=2.5 V@200 A/cm2,1.01 mΩ・cm2Output characteristicsJD (A/cm2)ID (A)VD (V)2502001501000.5 V1.5 V2.0 VVg=2.5 V1.0 V0.100.080.060.040.020.001.00.80.60.40.20.01.21 mΩ・cm2@ Vg=2.5 V, VB=1270V@Vg=-12 VY. Tanaka et al; ICSCRM 2007Y. Tanaka et al; ISPSD 2007, Korea (2007-6)Y. Tanaka et al; ICSCRM 2005, Pittsburgh (2005-9)① p+-gate layer formed by CVD layer growth method → Low gate resistance② Channel layer formed by the trench method Low concentration channel → Low pinch off voltage, high off gain③ Alignment free → Fine cell → Low on resistanceCharacteristics5000 VGSDp+ gate layern- drift layern+ substrateBlocking voltage (V)SiC-MOSFETSiC-JFET(SIT)GaN-HEMTOn resistance (mΩ・cm2)GaN limitSiC limitSi-SJ MOSSi limitSi-IGBT2001000800011040Cree'07Cree'07SiCED'07SiCED'03SiCED'02Hitachi'03Toshiba'03Toshiba'07Toshiba'03Hitachi'05Hitachi'07Sumitomo'07Furukawa'07Matsushita'07Mitsubishi'06AIST'06AIST'07Rohm'07Rohm'06AIST'06AIST'05AIST'05Semi South'07Rutgers Univ.'03North.Grumman'07SiCED'00Ryu'06Furukawa'07Fig. 9 Device structure of the IEMOSFET (implantation and epitaxial MOSFET) fabricated on the carbon face and its effectivenessThe surface on which the channel is formed is flattened using the epitaxial growth technology and the ion injection technology (AFM image), to improve the channel mobility.Fig. 10 Structure of buried gate type SIT and its static propertyAlthough it is normally on (it will not turnoff unless gate voltage is applied), the current-conducting loss is extremely low. The epitaxial growth technology also plays an important part in this device.Fig. 11 Trends in the on resistance and blocking voltage of the ampere class switchAIST has yielded top results in the world. For the recent trends in the Si devices of IGBT and J-MOS as well as the trends of the SiC power devices in the world, refer to “Technological innovation and application of power electronics taken to the next step” by Kazuo Arai in Ohm November 2009 issue in Japanese.

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