Vol.2 No.4 2010

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Research paper : Development of a real-time all-in-focus microscope (K. Ohba)−241−Synthesiology - English edition Vol.2 No.4 (2010) setting of the area size and the number of captured images, output of about one image per 2 sec. could only be obtained as the processing time. Since the MAPP2200 had ability to capture and process binary images at 2,000 to 3,000 images per second, the reasons for the slow processing speed were thought to be: 1) it was necessary to conduct sequential comparison by providing a reference voltage 256 times when capturing an image at 8 bit resolution, but the column A/D could not provide individual reference voltage for each pixel, and 2) the architecture of the SIMD processor was specialized for binary images.5 Second FS phaseHere, I shall explain the second FS phase for realizing Prototype 2 of the all-in-focus camera that allows real-time observation at 30 frames/sec..In the microscope system, we were able to obtain cooperation of Photron Ltd., a company with abundant experience in high-speed image capture. In this system, the camerahead of the high-speed video camera was used, and by using LVDS that allowed high-speed image transfer as the interface between the imaging mechanism and the image processing arithmetic circuit, the imaging mechanism and the image processing arithmetic circuit were separated. The commercially available high-speed imaging mechanism (high-speed video camera) and the image processing arithmetic circuit (FPGA) were used. It can be said that the road to product realization opened up widely by using the existing products.The configuration of Prototype 2 is shown in Fig. 15 and the external appearance is shown in Fig. 16. The output of the high-speed sensor goes through the CDS (correlated double sampling) and ADC, converted by the high-speed digital interface LVDS, and then transferred to the image-processing unit. Up to this point is the description of the part of the high-speed camera. LVDS is a standard interface for sending high rate image signals, and is a standard often used in digital LC displays. The saw-tooth generating circuit for the varifocal lens receives the synchronizing signals from the clock generator of the high-speed camera part, produces saw-tooth pulses at 30 Hz, and drives the lens with the lens-driving amp. In the image processing part, the IQM calculation and image compositing are accomplished with the input digital image signals, and outputted as VGA (video graphics array) signals. The 3D data is transferred to the PC by LVDS signals. At the PC, data is received by the LVDS capture board of the PCI bus.Mechanically, the focal distance movement used was the same as the one used in Prototype 1 and there was no problem. However, since the algorithm was implemented on the special vision chip in the first FS phase, it could not be transplanted directly to the FPGA, and it was necessary to modify the algorithm for FPGA. It was also necessary to use the internal memory to speed up the FPGA processing, and Fig. 13 Schematic diagram for the creation of all-in-focus image.Fig. 14 Example of VR display.Fig. 15 Block diagram for Prototype 2.Fig. 16 External appearance of Prototype 2.All-in-focus imageSingle focus imageHigh-speed sensorOptical systemVarifocal lensDACAmpClock Gen.,CDSADCAll-in-focus imageDepth imageVGA monitorPC interfaceLVDS

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