Shigeki Sakai (Leader) et al. of the Novel Electron Devices Group, the Nanoelectronics Research Institute (Director: Seigo Kanemaru) of the National Institute of Advanced Industrial Science and Technology (AIST) (President: Hiroyuki Yoshikawa) in collaboration with Ken Takeuchi, Associate Professor of the Graduate School of Engineering, the University of Tokyo (Univ. Tokyo) have demonstrated that the use of ferroelectric gate field-effect transistors (FeFETs) as memory cells dramatically improves the performance of NAND flash memory. The FeFET, the newly developed memory cell, can be programmed and erased as many times as 100 million or more and with programming voltage of less than 6 V, whereas the conventional NAND flash memory cells have ten thousand program/erase endurance cycles with approximately 20 V programming voltage. It has been assumed that conventional NAND flash memory can be downsized to 30 nm at the minimum, whereas this novel memory cell will meet the needs of the next 20-nm and 10-nm technology generations. And thus, this memory cell is expected to be used in a next-generation, high-density, high-capacity nonvolatile memory.
Results of the research was reported at the 23rd Nonvolatile Semiconductor Memory Workshop (the 23rd IEEE NVSMW / the 3rd ICMTD 2008) held in France, May 1822, 2008.