We have developed a new metal source–drain junction technology that can be applied to the transistors of 16-nm generation and beyond. In the very small metal-oxide-semiconductor (MOS) transistors of 16-nm generation and beyond, the parasitic resistance of the source–drain junction will become a big issue because it would ruin the improvement of the transistor performance. In addition, it is a big challenge to fabricate a source–drain junction accurately in transistors with a gate length in the order of 10 nm. The developed technology allows us to control the position of a very low-resistive metal source–drain junction at the sub-nanometer level. The control technology has been demonstrated to increase transistor performance significantly and should provide a solution to junction position control in the MOS transistors of 16-nm generation and beyond.