National Institute of Advanced Industrial Science and Technology (AIST)
Research resultsPublications > AIST TODAY > 2005-No.16
AIST TODAYNo.16 Spring 2005 [ PDF:17.6MB ]


High Accuracy Automatic Fitting for Next Generation Transistor Model HiSIM
- Cost Reduction for Development of Semiconductor Manufacturing Process through Application of Genetic Algorithm -

Masahiro Murakawa
Advanced Semiconductor Research Center
e-mail address

We have developed an automatic fitting method using the GA (Genetic Algorithm) for next generation transistor model HiSIM (Hiroshima University-STARC IGFET Model) to be used for circuit simulation in the development of advanced semiconductor manufacturing process. The fitting experiments were performed using MOSFET devices fabricated with the most advanced process (90 nm rule) provided by STARC. To accomplish the fitting, it took only a few hours using eight PCs, whereas it would typically take several days even for a skilled person. This technology will be commercialized by the Evolvable Systems Research Institute, Inc., a venture enterprise authorized by the AIST.

Figure
Fig. Fitting results for Ids-Vds characteristics of MOSFET: Lg(Channel length)=0.10um/Wg(Channel width)=2.0um. RMS errors for all devices were within only 2.5%.

Relational Information

AIST Today Vol.5,No3 (2005-No.16) 24



 back