Dr. Meishoku Masahara (left) and Dr. Eiichi Suzuki (right) of the Nanoelectronics Research Institute, who succeeded in the development of the world's thinnest vertical double-gate MOSFET

Fig.1 Possible orientations of the double-gate MOSFETs. We have succeeded in developing a vertical-type, double-gate MOSFET among the possible three types.

The new vertical double-gate MOSFET developed by AIST utilizes a commercially available bulk Si substrate. Fabrication of the world's thinnest channel was achieved by using the conventional CMOS fabrication technology and the newly discovered process where an etching rate by an alkaline solution is greatly retarded at the surface exposed to ion bombardment. With this new process, the group has succeeded both in fabricating a prototype of the world's thinnest vertical double-gate MOSFET featuring a channel thickness of 15mm and in providing the experimental proof of its double-gate performance. Actual measurements confirmed the superior electrical characteristics predicted by the theoretical evaluation. It can be said that this technology paves the way to the practical application of the double-gate MOSFET, or what is referred to as the ultimate MOSFET. These results were presented at the 2002 IEEE International Electron Devices Meeting (2002 IEDM) in December 2002 and generated great interest.

Newly Developed Ion-Bombardment-Retarded-Etching Process
The technological breakthrough in forming the extremely thin Si wall that acts as a vertically oriented channel is the newly discovered ion-bombardment-retarded-etching phenomenon (patent pending). The commercially available alkaline developing fluid (2.38% tetramethylammonium hydroxide) causes a significant retard in the etching rate for the Si substrate portions exposed to ion bombardment. Using these surfaces as etching masks, the group successfully formed a nanoscale wal l on a bulk silicon substrate that serves as a vertically-oriented channel. Firstly, a somewhat thicker wall with SiO₂ mask was fabricated on a (110)-oriented Si substrate (Fig. 2 (a)). Secondly, 30keV As ions were implanted, where the top and the bottoms of the Si wall were exposed to the keV ions, while the sidewalls remained unexposed (Fig.2 (b)). When the Si wall is dipped in a TMAH solution, the ion-exposed region worked as an etch-stopper and the Si wall was horizontally etched, ensuring a high level of control of the Si wall thinning. This method is excellent in both repeatability and practicability, enabling it to easily fabricate a Si wall channel thinner than that achieved using lithography without any RIE damage. In fact, this method has been applied to the development of the fabrication process of a vertical double-gate MOSFET (IMOSFET) with an ultrathin Si wall channel.

Fig.2 Flow chart of fabrication of an ultra-thin sillicon wall using the ion-bombardment-retarded-etching process, and SEM photos of the Si wall channel at each step: (a) thicker Si wall formation by SiO2 mask; (b) As-ion implantation after stripping the SiO2 mask; (c) ultrathin Si wall channel formation by using IBRE (wall thickness: 15nm).

Verifying Excellent Device Characteristics
A cross-sectional TEM image of the world's thinnest IMOSFET is shown in Fig. 3. The Si wall thickness is measured to be 15nm. The operation of the fabricated IMOSFET was verified and the experimental characteristics were precisely measured. Fig.4 shows the dependence of the gate threshold voltage (V_th) and subthreshold slope (S-slope) on the Si channel thickness, both of which are the important indicators of the performance of the MOSFET. S-slope is he necessary gate voltage when a drain current increases by one decade in the subthreshold region. The theoretical S-slope at room temperature is 60mV/decade. The prominent short-channel effects are the increase in the S-slope which means degrading drain current stand-up against a gate voltage and the threshold roll-off to the negative direction in case of n-channel. These effects can be effectively diminished by thinning of the Si channel, thus proving the superior characteristics of the double-gate MOSFET. It can be concluded, therefore, that the short-channel effects are sufficiently suppressed by making the Si-channel thickness less than 20nm as shown in Fig.4. This means that the characteristics of the device do not degrade but is rather improved by further scaling-down of the circuit elements. The finding is certainly a major advance in the realization of ultra-high density ULSIs in the future. The experimental results of the fabricated IMOSFET indicate that the S-slope degradation can be effectively inhibited even in the device with a ultra-short channel, meaning that less drain current is required to turn on the device. Hence, the device contributes to less power consumption while the system is in operation. Furthermore, each of the two gates can be utilized to control the gate threshold voltage of one another. This function to optimally control the threshold voltage is an advantage for the power reduction.

Fig.3 Cross-sectional TEM image of the fabricated world's thinnest vertical double-gate MOSFET (IMOSFET) with a wall channel thickness of 15nm

Fig.4 Gate threshold voltage (Vth) of the fabricated IMOSFET, and S-slope as a function of the Si wall channel thickness. Circles and squares indicate the values under the saturation mode and linear mode, respectively. Smaller S-slope and Vth mean that the shor-channel behavior is suppressed.

Future Prospects
These results have led to the establishment of a basic fabrication technology for scaled vertical MOSFETs(IMOSFETs) using a bulk silicon substrate. The newly developed IMOSFET fabrication technology has the following strong points and is expected to be applied to practical use: (1) utilization of ion-bombardment-retarded etching process to fabricate the thinnest Si wall without any process damage; (2) fabrication of a thinner wall than using lithography; (3) easy scaling to the level of nm by controlling the height of the Si wall; (4) a vertically shaped channel capable of carrying a high electric current; (5) allowing the introduction of a High-K gate dielectric material.

Future plans include improving device characteristics through optimization of the processes, establishing ULSI technology for ultra-low power, and multiple applications of the device, making the most of the features of the double-gate MOSFET as a 4-terminal device.

Further Information Further information can be obtained from: Meishoku Masahara Eiichi Suzuki (deputy-director) Electronics Research Institute, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan